Mar 22 2018
Mensaje Privado
1 Punto2 Puntos3 Puntos4 Puntos5 Puntos Sin valoracion
105 visitas

Cadence Allegro and OrCAD 17.20.000-2016 HF035 | 2.6 Gb

Cadence Design Systems, Inc. has released an update (HF035) to OrCAD Capture, PSpice Designer and PCB Designer 17.20.000-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.

Fixed CCRs: SPB 17.20.000-2016 HF035[/url] 1873547 ADW ADW_UPREV adw_uprev resulted in incomplete footprint XML
1643895 ADW DBEDITOR Create Footprint model name is not working properly if footprint exists in local flatlib
1846400 ADW DBEDITOR ‘Copy As’ and ‘Rename’ STEP model options do not work
1868299 ADW FLOW_MGR Copy Project fails and makes Flow Manager unresponsive
1872796 ADW PART_BROWSER Part/Model Details Attributes are all empty when connected to the EDM DB
1877199 ALLEGRO_EDITOR DATABASE Purging backdrill adds bottom filmmask to vias when it is not defined in the padstack
1877219 ALLEGRO_EDITOR DRC_CONSTR Allegro Crash at DRC Update
1875528 ALLEGRO_EDITOR GRAPHICS Subclasses disappear in partition
1868364 ALLEGRO_EDITOR OTHER Translator for Layout to PCB Editor fails in release 17.2-2016 but works in 16.6
1822989 ALLEGRO_EDITOR UI_GENERAL Allegro very slow
1855275 ALLEGRO_EDITOR UI_GENERAL Allegro becomes slow if OpenGL disabled
1868803 ALLEGRO_EDITOR UI_GENERAL Infinite Cursor misbehave
1869523 ALLEGRO_EDITOR UI_GENERAL PCB Editor hangs inconsistently on axlOpenDesign
1871409 ALLEGRO_EDITOR UI_GENERAL ESC key does not function with Enable_command_window_history set
1812306 ALLEGRO_PROD_TOOLB CORE Incorrect DIFF result of PCB Design Compare
1872772 ASDA MISCELLANEOUS SDA pulls a license for ‘Allegro_performance’
1877070 CAPTURE OTHER Capture redraws icons
1863624 CONCEPT_HDL CONSTRAINT_MG XNet names are changed in the designs migrated to release 17.2-2016
1866290 CONCEPT_HDL CORE variant editor/DE-DHL crashed when changing a component property
1858139 CONCEPT_HDL OTHER Slow graphic response in Windows10: Icons redraw
1872703 CONCEPT_HDL OTHER Icon and toolbar in DE-HDL keeps on refreshing for every command
1873949 CONCEPT_HDL OTHER DE-HDL user interface refreshes frequently
1871542 CONSTRAINT_MGR INTERACTIV Extracting object with ‘Referenced ECSet’ does not inherit T-points from the applied ECSet
1868812 CONSTRAINT_MGR UI_FORMS Cannot Save Log File from CM ECSet Audit.
1878574 ECW PROJECT_MANAG Duplicate entries are created in SharePoint users list while creating project on SSO setup
1878619 ECW PROJECT_MANAG Too many mails generated on doing create project
1862772 ECW TDO-SHAREPOIN Logical BOM file name not displayed in Changed Files of Pulse Activity Log.
1860641 INSTALLATION DOWNLOAD_MGR Download Manager remembers credential settings
1867195 INSTALLATION DOWNLOAD_MGR Download manager crash
1872187 SIP_LAYOUT DRC_CONSTRAIN Sliding a cline removes DRC markers but updating DRC shows more DRC markers
About Allegro and OrCAD 17.2-2016. The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
– OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
– New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.
– New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
– OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors’ productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
– OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
– PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.

Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located

About Hot-Fix. A Hot-Fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack. Unlike Service Packs (SP), which are scheduled, periodic releases, Hot-Fix releases are not periodically scheduled. Simply requesting a Hot-Fix does not automatically guarantee that the customer will receive it: all Hot-Fix requests first must be approved and accepted by Cadence prior to delivery. Furthermore, a Hot-Fix may contain fixes related to problems reported earlier by different customers. All the files included in the Hot-Fix will nevertheless be installed.

About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.

Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF035
Supported Architectures: x64
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above
Size: 2.6 Gb




Don’t forget to say Thanks !!!

Dl4Evr es author

A creado 3305 posts en Omaredomex.

Deja un Comentario